1. Field of the Invention
The invention relates generally to the calibration of a test unit utilized for characterizing CML integrated circuits, and more particularly, the invention relates to calibration apparatus for a test unit for characterizing CML integrated circuits which determines the time delays present in the test unit prior to testing the CML circuits.
2. Description of the Prior Art.
It is desirable to fully, accurately characterize the propagation time delays of integrated current mode logic (hereinafter referred to as CML) integrated circuits and integrated circuits generally. Therefore, it is necessary to know any time delays which result from the test apparatus associated with CML circuit. The time delays associated with the test apparatus must be removed from the total time delay in order to accurately determine the time delays associated with the CML integrated circuit itself. Because of the complexity of large scale integrated circuits it is desirable that the calibration apparatus for the test unit be automated and relatively simple in nature.
The basic CML circuit is a constant current source applied to the emitters of two transistors. The base of one transistor is connected to a reference voltage source and the base of the other transistor is connected to the input signal which is designed to actuate the switching circuit. The collectors of both transistors are tied through resistors to ground. The output of the basic CML switching circuit can be considered to be at either or both of the collectors of the two transistors. The voltage on the output of the collector having the reference voltage applied thereto is considered to be the true output and the collector voltage of the other transistor is considered to be the complement. This basic circuit can be utilized to construct the various digital logic devices known in the art. For example, it can be utilized to construct AND gates, OR gates, registers, etc.
In order to properly design digital systems it is necessary that the propagation time delays and the transition times along with the other characteristics of the integrated circuits employed in the design be known to the designer. Therefore, accurate testing of the CML integrated circuits is necessary. Further, it is desirable that any time delays due to the test apparatus itself be accurately known so that these time delays can be removed from the time delays determined while testing the CML circuit to determine the time delays associated with the CML circuit itself. Increased accuracy of the characterization of the CML circuit results in the increased likelihood that the final design utilizing the CML circuits will operate as desired.
The prior constructions of CML testing apparatus do not shown the calibration apparatus for a test apparatus utilizing a power splitter and a relay matrix in conjunction with a shorting device.